1. Field of the Invention
This invention relates to methods of fabricating semiconductor devices, and more specifically, to methods of forming self-aligned high density electrodes or contacts to devices formed through the use of anisotropic etching, commonly referred to by the term V-groove technology, to provide recesses in semiconductor substrates which contain active devices or other associated elements.
2. Description of the Prior Art
For many years since the initial development of integrated circuit technology great efforts have been made to provide an ever increasing number of components, and thus their associated functions, on a single integrated circuit chip. Techniques to increase component density have always received great attention in the semiconductor industry. One of the technologies, recently adapted for providing increased density, utilizes recesses etched in the surface of a semiconductor substrate to enable fabrication of devices having vertical geometric features, thus reducing the lateral area required for layout of devices.
Although use of vertical device structures were proposed as early as 1956, see U.S. Pat. No. 2,980,830 to Shockley, it was not until recent years that available photolithographic limitations provided a barrier to density improvements in conventional planar integrated circuits. Vertical integration techniques, particularly in metal, oxide, semiconductor field-effect transistor (MOSFET) logic circuit design, provide desirable increases in density. See, for example, the article, "Grooves Add New Dimension to V-MOS Structure and Performance," F. B. Jenne, Electronics, Aug. 18, 1977, pp. 100-106. Further improvements in density in V-MOS technology using state of the art photolithographic processing are again limited by alignment tolerances as illustrated in FIG. 1 representing a typical prior art V-MOSFET.
Referring to FIG. 1, a V-MOSFET is shown in which a semiconductor substrate 10 of p-type material has a relatively thick thermal oxide layer 12 grown on its upper surface. A rectangular hole having a width y is etched in layer 12 exposing the surface of substrate 10. An n-type dopant such as arsenic or phosphorous is diffused through the hole to form a highly doped n-type region. Next, any oxide covering the n-type region is removed and a V-shaped notch or groove is anisotropically etched into substrate 10. By providing a substrate having its main surfaces parallel to the 100 plane of crystallinity, well known anisotropic etchants will etch preferentially along the 111 direction to form a self-stopping V-groove. Due to lateral diffusion of the n-type dopant, portions of the original n-type region remain as regions 14 and 16, subsequently to become the source and drain of the V-MOSFET. Next, a thin gate dielectric 18 is grown in the V-groove. Up to this point in the process it is possible to use only a single photoresist step and associated mask, as both the source, drain and V-groove may be formed in a self-aligned manner by a single photolithographic etching step which was used to form the initial hole in thick oxide 12. By using minimum mask geometry a very small device has been partially defined. In order to complete the V-MOSFET, however, a gate electrode 20 is required which must be defined by a second photolithographic masking step. In order to insure proper positioning of the gate electrode, it is normally necessary to account for any mask alignment tolerances required between the registration of the gate forming mask and the mask previously used to define the remainder of the FET. In a process having a mask alignment error of .+-.d, in order to ensure proper coverage of the gate electrode, a minimum mask dimension x for the gate electrode must be equal to y+2d. Thus the minimum overall device dimension becomes y+2d, even though a substantial portion of the V-MOSFET has been fabricated using the minimum photolithographic dimension y. Techniques for providing a self-aligned gate electrode in such a process would enable further increases in density to be achieved. However, prior art techniques suitable for forming a self-aligned electrode within a recess such as a V-groove, all have decided disadvantages.
One prior art technique for forming a self-aligned electrode in a recess is illustrated in the article, "Making Conductive Platinum Membranes Across Holes in Silicon Without the Use of Masks," by P. Geldermans, IBM Technical Disclosure Bulletin, Vol. 19, No. 10, March 1977, pp. 3957-8. Here a thin conductive layer is deposited over a substrate containing a selectively etchable layer on its surface, except where the recess is to be provided. After deposition of the conductive layer the etchable layer is removed so that the overlying conductive layer is physically torn apart near the edges of the recess leaving the conductive layer only in the recess. The use of such lift-off techniques is highly dependent on the physical characteristics of the deposited conductive layer and has been found to have other undesirable processing limitations.
Another technique taught in U.S. Pat. No. 3,998,673 to Chow provides a self-aligned solid triangular-shaped electrode in an anisotropic V-groove by depositing a thick layer of polycrystalline semiconductor (polysilicon) entirely filling the V-groove and covering the surface of the substrate. Excess polysilicon and protective surface oxide are removed by lapping or polishing these layers flush with the surface of the substrate to provide a triangular-shaped polysilicon portion within the original substrate surface. Control of lapping processes is extremely difficult and the process provides a solid polysilicon layer, which may be undesirable for V-MOSFET applications.
A related technique is apparently used, but not described in detail, in the article, "Optimization of Nonplanar Power MOS Transistors," by K. P. Lisiak et al, IEEE Transactions on Electron Devices, Vol. ED-25, No. 10, October 1978, pp. 1229-34. There in FIG. 7(d) there is shown a self-aligned gate electrode for a V-MOSFET which is apparently formed by lapping the surface of the partially completed device to planarize the upper edges of the gate electrode with the surface of the substrate.
A similar isolated polysilicon structure and method are taught in U.S. Pat. No. 4,120,744 to Payne et al. Here a triangular section of polysilicon is provided in an oxidized V-groove by selectively etching a thick polysilicon layer overlying both V-grooves and the substrate to a level below the surface of the substrate. In an alternative technique, illustrated in FIGS. 9-19, a thin layer of polysilicon is provided over an oxide protected surface containing V-grooves. After the thin oxide layer is provided over the polysilicon, a layer of photoresist is provided which is then patterned to leave a thin layer of photoresist over a portion of the polysilicon entirely within the oxide covered V-grooves. Next the exposed oxide and polysilicon layers are selectively etched leaving the photoresist-protected silicon dioxide and polysilicon within the V-grooves. This last technique is difficult to execute, as the mask, not described, to pattern the photoresist must be aligned within the recessed portion of the V-grooves. Use of the technique inherently requires that the V-groove be formed using a mask having openings for the V-grooves substantially larger than the minimum photolithographic dimensions.
Other references believed to be related to the subject invention include the following documents. The article, "Method for Forming Phase Lines," by R. R. Garnache, IBM Technical Disclosure Bulletin, Vol. 19, No. 7, December 1976, pp. 2471-2, which teaches the selective etching of raised portions of conductive polysilicon lines passing over an undulating substrate by applying a relatively thick layer of photoresist over the substrate, ion implanting conductivity determing impurities to a depth sufficient to penetrate the thickness of only the raised portions of the polysilicon lines, removing the photoresist and selectively etching those raised portions of the polysilicon in preference to those portions not ion implanted to yield polysilicon lines only in those regions of the substrate which were initially not raised. The article, "Forming Sidewall Dielectric Isolation of Integrated Circuit Devices," by P. M. Schaible et al, IBM Technical Disclosure Bulletin, Vol. 17, No. 10, March 1975, pp. 2893-4, is of interest as it teaches the use of dry reactive ion etching of a thick organic polymer layer overlying a substrate containing V-grooves in order to planarize the surface of the substrate leaving polymer filled V-grooves. The article, "Isolation of Device Components," G. T. Galyon, IBM Technical Disclosure Bulletin, Vol. 18, No. 6, November 1975, pp. 1854, is of interest as it teaches a method of forming dielectrically isolated regions in a semiconductor substrate in which a photoresist is illustrated as only partially filling an etched groove in the substrate. However, no process is disclosed as to how such a configuration is obtainable. Co-pending U.S. patent application, Ser. No. 973,219, entitled, "Method for Reducing Parasitic Capacitance in Integrated Circuit Structures," of W. P. Noble et al, filed on Dec. 26, 1978, now U.S. Pat. No. 4,222,816, may also be of interest as it teaches the removal of the raised portions of conductive polysilicon lines by the uniform removal of a thick layer of photoresist to expose only the tops of the raised portions of the polysilicon lines, which are subsequently etched. Finally, U.S. Pat. No. 4,163,988 to Yeh et al is of interest as it illustrates V-MOSFET devices having conductive polysilicon electrodes which terminate within a V-groove below the surface of a substrate, but does not teach how such a structure may be formed.